1. Field of Invention
The present invention relates to a processing method and processing apparatus for network packets. More particularly, the present invention relates to a network packet storage method and network packet transmitting apparatus using the same.
2. Description of Related Art
Nowadays, with the rapid development of the Internet, the network congestion problem is increasingly severe, which significantly brings down the network quality of service. Generally, the existing switches or routers use an embedded or external Static Random Access Memory (SRAM) as the packet buffer area, mainly because the required capacity of the packet buffer area is not necessarily large when the network speed is not rapid or there are not many switches/routers and the so-called Quality of Service (QoS) is not supported. Moreover, the access timing of the SRAM is better than that of the Dynamic Random Access Memory (DRAM). Thus, the SRAM is used widely.
However, if the speed of each port reaches Gigabit or 10 Gigabits, and 16 or more ports are to be supported, and the so-called Jumbo Frame support and QoS need be considered, since more processes are to be performed on the packet data, the time for the packet remaining in the switch becomes longer, which means the amount of the packet data to be stored is very large, and thus a larger memory is required to store the data. At this time, the DRAM is a good option.
However, in terms of the access characteristic of the DRAM, if the Row Address is to be changed each time when the DRAM is accessed, it takes some time to perform Active Bank/Row, pre-charge and the like. Therefore, with respect to this characteristic, there are two common approaches.
In the first approach, a plurality of DRAM controllers are used for controlling a plurality of DRAM modules, and a scheduling controller is used for managing the Overhead Accesses required by each DRAM, such as active bank/row, pre-charge and the like. Except for the DRAMs which are performing these overhead accesses, other DRAMs are assigned to be used by the system. The problem ramified therefrom is that too many DRAM controllers are used, which does not follow the economical and practical principles of implementing the circuit.
The second approach is to use a single DRAM and a single DRAM controller; however, in this approach, the basic overhead access time is still required, and an Arbiter Controller is used to arrange the access of each Bank. During the reading and writing operations of the internal circuit, for the access to the same row, the access bandwidth of an unused bank is wasted, and thus the arbiter controller assigns and arranges the user with a higher priority to access the access space of the bank. However, the approach also causes the written and read packet data to form discrete segments. In order to incorporate and read out the packet data in different segments normally, much additional information is required to record the exact address of data in each segment on the DRAM.